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Digital systems testing and testable design Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman.

Contributor(s): Material type: TextTextSeries: Electrical engineering communications and signal processing seriesPublication details: Mumbai : Jaico Publishing House, 2013.Description: xviii, 652 p. : ill. ; 25 cmISBN:
  • 8172248911 (Pbk)
  • 9788172248918
Subject(s): DDC classification:
  • 621.3815 D569 23
LOC classification:
  • TK7874 .A23 1990
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Item type Current library Collection Call number Status Notes Date due Barcode
Books Books Central Library, IISER Bhopal Reference Section Reference 621.3815 D569 (Browse shelf(Opens below)) Not For Loan Reserve 9066
Books Books Central Library, IISER Bhopal General Section 621.3815 D569 (Browse shelf(Opens below)) Available 9067
Browsing Central Library, IISER Bhopal shelves, Shelving location: Reference Section, Collection: Reference Close shelf browser (Hides shelf browser)
621.3815 C457L3 Linear integrated circuits 621.3815 C457L4 Linear Integrated circuits 621.3815 C457L4 Linear Integrated circuits 621.3815 D569 Digital systems testing and testable design 621.3815 L972N Near-equilibrium transport : 621.3815 L972N Nanoscale transistors : 621.3815 P34P Power aware design methodologies

Includes bibliographical references (p. 644-645) and index.

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