MARC details
| 000 -LEADER |
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05478nam a22004333i 4500 |
| 001 - CONTROL NUMBER |
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EBC5173739 |
| 003 - CONTROL NUMBER IDENTIFIER |
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MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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20210921154944.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
210914s2012 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780273775461 |
| Qualifying information |
(electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| Cancelled/invalid ISBN |
9780273764526 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(MiAaPQ)EBC5173739 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(Au-PeEL)EBL5173739 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaPaEBR)ebr11479769 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)1015868550 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
MiAaPQ |
| Language of cataloging |
eng |
| Description conventions |
rda |
| -- |
pn |
| Transcribing agency |
MiAaPQ |
| Modifying agency |
MiAaPQ |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Mano, M. Morris. |
| 245 10 - TITLE STATEMENT |
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| Title |
Digital Design. |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
5th ed. |
| 264 #1 - |
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Harlow, United Kingdom : |
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Pearson Education Limited, |
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2012. |
| 264 #4 - |
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©2012. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
1 online resource (564 pages) |
| 336 ## - |
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text |
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txt |
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rdacontent |
| 337 ## - |
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computer |
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c |
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rdamedia |
| 338 ## - |
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online resource |
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cr |
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rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Cover -- Contents -- Preface -- 1 Digital Systems and Binary Numbers -- 1.1 Digital Systems -- 1.2 Binary Numbers -- 1.3 Number-Base Conversions -- 1.4 Octal and Hexadecimal Numbers -- 1.5 Complements of Numbers -- 1.6 Signed Binary Numbers -- 1.7 Binary Codes -- 1.8 Binary Storage and Registers -- 1.9 Binary Logic -- 2 Boolean Algebra and Logic Gates -- 2.1 Introduction -- 2.2 Basic Definitions -- 2.3 Axiomatic Definition of Boolean Algebra -- 2.4 Basic Theorems and Properties of Boolean Algebra -- 2.5 Boolean Functions -- 2.6 Canonical and Standard Forms -- 2.7 Other Logic Operations -- 2.8 Digital Logic Gates -- 2.9 Integrated Circuits -- 3 Gate-Level Minimization -- 3.1 Introduction -- 3.2 The Map Method -- 3.3 Four-Variable K-Map -- 3.4 Product-of-Sums Simplification -- 3.5 Don't-Care Conditions -- 3.6 NAND and NOR Implementation -- 3.7 Other Two-Level Implementations -- 3.8 Exclusive-OR Function -- 3.9 Hardware Description Language -- 4 Combinational Logic -- 4.1 Introduction -- 4.2 Combinational Circuits -- 4.3 Analysis Procedure -- 4.4 Design Procedure -- 4.5 Binary Adder-Subtractor -- 4.6 Decimal Adder -- 4.7 Binary Multiplier -- 4.8 Magnitude Comparator -- 4.9 Decoders -- 4.10 Encoders -- 4.11 Multiplexers -- 4.12 HDL Models of Combinational Circuits -- 5 Synchronous Sequential Logic -- 5.1 Introduction -- 5.2 Sequential Circuits -- 5.3 Storage Elements: Latches -- 5.4 Storage Elements: Flip-Flops -- 5.5 Analysis of Clocked Sequential Circuits -- 5.6 Synthesizable HDL Models of Sequential Circuits -- 5.7 State Reduction and Assignment -- 5.8 Design Procedure -- 6 Registers and Counters -- 6.1 Registers -- 6.2 Shift Registers -- 6.3 Ripple Counters -- 6.4 Synchronous Counters -- 6.5 Other Counters -- 6.6 HDL for Registers and Counters -- 7 Memory and Programmable Logic -- 7.1 Introduction -- 7.2 Random-Access Memory. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
7.3 Memory Decoding -- 7.4 Error Detection and Correction -- 7.5 Read-Only Memory -- 7.6 Programmable Logic Array -- 7.7 Programmable Array Logic -- 7.8 Sequential Programmable Devices -- 8 Design at the Register Transfer Level -- 8.1 Introduction -- 8.2 Register Transfer Level Notation -- 8.3 Register Transfer Level in HDL -- 8.4 Algorithmic State Machines (ASMs) -- 8.5 Design Example (ASMD Chart) -- 8.6 HDL Description of Design Example -- 8.7 Sequential Binary Multiplier -- 8.8 Control Logic -- 8.9 HDL Description of Binary Multiplier -- 8.10 Design with Multiplexers -- 8.11 Race-Free Design (Software Race Conditions) -- 8.12 Latch-Free Design (Why Waste Silicon?) -- 8.13 Other Language Features -- 9 Laboratory Experiments with Standard ICs and FPGAs -- 9.1 Introduction to Experiments -- 9.2 Experiment 1: Binary and Decimal Numbers -- 9.3 Experiment 2: Digital Logic Gates -- 9.4 Experiment 3: Simplification of Boolean Functions -- 9.5 Experiment 4: Combinational Circuits -- 9.6 Experiment 5: Code Converters -- 9.7 Experiment 6: Design with Multiplexers -- 9.8 Experiment 7: Adders and Subtractors -- 9.9 Experiment 8: Flip-Flops -- 9.10 Experiment 9: Sequential Circuits -- 9.11 Experiment 10: Counters -- 9.12 Experiment 11: Shift Registers -- 9.13 Experiment 12: Serial Addition -- 9.14 Experiment 13: Memory Unit -- 9.15 Experiment 14: Lamp Handball -- 9.16 Experiment 15: Clock-Pulse Generator -- 9.17 Experiment 16: Parallel Adder and Accumulator -- 9.18 Experiment 17: Binary Multiplier -- 9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs -- 10 Standard Graphic Symbols -- 10.1 Rectangular-Shape Symbols -- 10.2 Qualifying Symbols -- 10.3 Dependency Notation -- 10.4 Symbols for Combinational Elements -- 10.5 Symbols for Flip-Flops -- 10.6 Symbols for Registers -- 10.7 Symbols for Counters -- 10.8 Symbol for RAM -- Appendix. |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Answers to Selected Problems -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- Q -- R -- S -- T -- U -- V -- W -- X. |
| 588 ## - |
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| -- |
Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) |
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| Local note |
Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2021. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 655 #4 - INDEX TERM--GENRE/FORM |
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| Genre/form data or focus term |
Electronic books. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Ciletti, Michael D. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Print version: |
| Main entry heading |
Mano, M. Morris |
| Title |
Digital Design: International Editions |
| Place, publisher, and date of publication |
Harlow, United Kingdom : Pearson Education Limited,c2012 |
| International Standard Book Number |
9780273764526 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) |
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| Corporate name or jurisdiction name as entry element |
ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="https://ebookcentral.proquest.com/lib/iiserb/detail.action?docID=5173739">https://ebookcentral.proquest.com/lib/iiserb/detail.action?docID=5173739</a> |
| Public note |
Click to View |